XC4008E-2PQ160C

high-performance, high-capacity, Field Programmable Gate Array, QFP, 80MHz

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Price:: US $23.90~31.07 / piece [Get Latest Price]

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Qty (lots)	Price/lot
1 ~ 2 :	31.07 / Piece
2 ~ 334 :	23.90 / Piece

PartNumber:: XC4008E-2PQ160C

Brand:: Xilinx Inc - Xilinx | D/C: 00+

Availability:: Supply Ability: 1/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

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Products Upload time: 2013-06-17

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Part Number:XC4008E-2PQ160C
US $23.90 - 31.07
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piece

Product Summary

The XC4008E-2PQ160C is a high-performance, high-capacity Field Programmable Gate Array. The XC4008E-2PQ160C provides the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, the XC4008E-2PQ160C combines architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.

Parametrics

XC4008E-2PQ160C general specifications: (1)logic cells:770; (2)max logic gates(NO RAM):8000; (3)max. RAM bits(No logic):10368; (4)typical gate range:6000 to 15000; (5)CLB matrix:18*18; (6)total CLBs:324; (7)Number of filp-flops:936; (8)max. user I/O:144.

Features

XC4008E-2PQ160C features: (1)Fully PCI compliant (speed grades -2 and faster); (2)Abundant fiip-flops; (3)Flexible function generators; (4)Dedicated high-speed carry logic; (5)Wide edge decoders on each edge; (6)Hierarchy of interconnect lines; (7)Internal 3-state bus capability; (8)Eight global low-skew clock or signal distribution networks; (9)System Performance beyond 80 MHz; (10)Flexible Array Architecture; (11)Low Power Segmented Routing Architecture; (12)Interfaces to popular design environments; (13)Fully automatic mapping, placement and routing; (14)Interactive design editor for design optimization.