EPM7064SLC44-5N

PLD, PLCC, –2.0 to 7.0 V

Rated 5 Rating 5 | reviews | Write a review

Price:: US $3.50~4.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $3.50~4.00

PartNumber:: EPM7064SLC44-5N

Brand:: Altera Corporation - ALTR | Pack: PLCC | D/C: 07+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. hellen's store

(Hong Kong)

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-07-12

From Other Seller

Part Number:EPM7064SLC44-5N
US $3.50 - 4.00
EKXG401ELL6R8MJ16S

US $5.00 - 5.00 / Piece
(0) Remove
EKZE250ELL152MK25S

US $0.10 - 1.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM7064SLC44-5N high-density, high-performance PLD is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064SLC44-5N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. The EPM7064SLC44-5N in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM7064SLC44-5N absolute maximum ratings: (1)Supply voltage: –2.0 to 7.0 V With respect to ground; (2)DC input voltage –2.0 to 7.0 V; (3)DC output current, per pin –25 to 25 mA; (4)Storage temperature No bias –65 to 150 ℃; (5)Ambient temperature Under bias –65 to 135 ℃; (6)Junction temperature: 150 ℃ at Ceramic packages, under bias, 135 ℃ at PQFP and RQFP packages, under bias.

Features

EPM7064SLC44-5N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices-ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S; (5)devices with 128 or more macrocells; (6)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (7)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (8)PCI-compliant devices available.