MPC8540CVT667JB

MPC8540CVT667JB, integrated processor, 3.63 V, 10.4 MHz, 10 μA, BGA

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Price:: US $170.00~221.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
1 ~ 2 :	221.00 / Piece
2 ~ 5 :	170.00 / Piece

PartNumber:: MPC8540CVT667JB

Brand:: Freescale Semiconductor, Inc - Freescale | D/C: 06+

Availability:: Supply Ability: 1/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-05-14

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Part Number:MPC8540CVT667JB
US $170.00 - 221.00
Quantity:

piece

Product Summary

The MPC8540CVT667JB is an integrated processor. The MPC8540CVT667JB integrates a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8540CVT667JB combines system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8540CVT667JB PowerQUICC III Integrated Host Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office.

Parametrics

MPC8540CVT667JB absolute maximum ratings: (1)For devices rated at 1 GHz:–0.3 V to 1.43 V; (2)For devices rated at 1 GHz AVDD:–0.3 V to 1.43 V; (3)DDR DRAM I/O voltage GVDD:–0.3 V to 3.63 V; (4)Three-speed Ethernet I/O voltage LVDD –0.3 to 3.63 V PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII OVDD –0.3 to 3.63 V; (5)Input voltage DDR DRAM signals MVIN:–0.3 V to (GVDD + 0.3)V; (6)DDR DRAM reference MVREF:–0.3 V to (GVDD + 0.3)V; (7)Storage temperature range TSTG:–55°C to 150 °C.

Features

MPC8540CVT667JB features: (1)Full ECC support on 64-bit boundary in both cache and SRAM modes; (2)Cache mode supports instruction caching, data caching, or both; (3)External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing); (4)Eight-way set-associative cache organization (1024 sets of 32-byte cache lines); (5)Supports locking the entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions; (6)Global locking and flash clearing done through writes to L2 configuration registers; (7)Instruction and data locks can be flash cleared separately; (8)Read and write buffering for internal bus accesses.