CX28250-26

ATM-SONET Physical Layer (PHY), –0.5 to +4.6V, PLL clock and data recovery (CDR) circuit, 156 pin BGA

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Price:: US $10.00~12.00 / piece [Get Latest Price]

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	US $10.00~12.00

PartNumber:: CX28250-26

Brand:: Mindspeed Technologies, Inc. - MNDSPEED | Pack: BGA | D/C: 03+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-09-06

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Part Number:CX28250-26
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Product Summary

The CX28250-26 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This CX28250-26 has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and optional enhanced feature sets for ATM-WAN access applications. It provides ATM Forum-compliant service termination, and maps the 53-byte cells from an ATM switch fabric or an adaptation layer processor (SAR) into the SONET payload. The CX28250-26 is tailored to meet a wide variety of ATM OC-3 applications. These include WAN terminals, ATM LAN and WAN switches, ATM OC-3 NICs, and Ethernet-ATM uplink cards.

Parametrics

CX28250-26 absolute maximum ratings: (1)Supply Voltage: –0.5 to +4.6V; (2)VGG Pin: +6.0V; (3)Storage Temperature –40℃ to 125℃; (4)Lead Temperature: +240℃ for 10 sec; (5)Junction Temperature: +125℃; (6)Static Discharge Voltage, Human Body Model: ±1500V @ 25℃; (7)Static Discharge Voltage—Charged Device Model: ±400V @ 25℃; (8)Latch-up Current: ±400 mA @ 25℃; (9)FIT Rate Value: TBD; (10)θJA: 40 ℃/W with no airflow,36 ℃/W at 1.5 m/s airflow; (11)θJC: 6.5 ℃/W.

Features

CX28250-26 features: (1)Tested APS software driver available from Mindspeed; (2)Synthesizes a 155.52 MHz clock from an 19.44 MHz input; (3)UTOPIA Level 2 interface; (4)Meets ITU, ANSI, and ATM Forum standards; (5)ATM Forum WIRE interface for PMDs using PECL; (6)D1-D3, D4-D12 external data link; (7)Supports APS (K1/K2 bytes); (8)Line Fail and Path Fail outputs; (9)SRAM-style microprocessor interface for all control and configuration registers; (10)Glueless interface to the CN823x segmentation and reassembly devices; (11)JTAG (IEEE 1149.1a-1993) compliant; (12)8 kHz and 19.44 MHz selectable sync outputs; (13)SONET overhead processing; (14)Automatic collection of one-second statistics; (15)Low power consumption-500 mW; (16)3.3 V, (–40℃ to 85℃); (17)Package: 156 pin BGA.