(Hong Kong)
Product Summary
The IDT71V65603S133PFGI is a 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAM. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
Parametrics
IDT71V65603S133PFGI absolute maximum ratings: (1)VTERM, Terminal Voltage with Respect to GND: -0.5 to +4.6 V; (2)VTERM, Terminal Voltage with Respect to GND: -0.5 to VDD V; (3)VTERM, Terminal Voltage with Respect to GND: -0.5 to VDD +0.5 V; (4)VTERM, Terminal Voltage with Respect to GND: -0.5 to VDDQ +0.5 V; (5)TA, Commercial Operating Temperature: -0 to +70℃; (6)Industrial Operating Temperature: -40 to +85℃; (7)TBIAS Temperature Under Bias: -55 to +125℃; (8)TSTG Storage Temperature: -55 to +125℃; (9)PT Power Dissipation: 2.0 W; (10)IOUT DC Output Current: 50 mA.
Features
IDT71V65603S133PFGI features: (1)256K × 36, 512K × 18 memory configurations; (2)Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access); (3)ZBTTM Feature - No dead cycles between write and read cycles; (4)Internally synchronized output buffer enable eliminates the need to control OE; (5)Single R/W (READ/WRITE) control pin; (6)Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications; (7)4-word burst capability (interleaved or linear); (8)Individual byte write (BW1 - BW4) control (May tie active); (9)Three chip enables for simple depth expansion; (10)3.3V power supply (±5%); (11)3.3V I/O Supply (VDDQ); (12)Power down controlled by ZZ input; (13)Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array(fBGA).
Diagrams
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