Product Summary
The IS61C1024-15J is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM. The device is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the IS61C1024-15J assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C1024-15J is available in 32-pin 300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I, 8 x 13.4) packages.
Parametrics
IS61C1024-15J absolute maximum ratings: (1)VTERM, Terminal Voltage with Respect to GND: –0.5 to +7.0 V; (2)TBIAS, Temperature Under Bias: –55 to +125 ℃; (3)TSTG, Storage Temperature: –65 to +150 ℃; (4)PT, Power Dissipation: 1.5 W; (5)IOUT, DC Output Current (LOW): 20 mA.
Features
IS61C1024-15J features: (1)High-speed access time: 12, 15, 20, 25 ns; (2)ow active power: 600 mW (typical); (3)Low standby power: 500 mW (typical) CMOS standby; (4)Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications; (5)Fully static operation: no clock or refresh required; (6)TTL compatible inputs and outputs; (7)Single 5V (±10%) power supply; (8)Low power version available: IS61C1024L; (9)Commercial and industrial temperature ranges available.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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IS61C1024-15JI |
IC SRAM 1MBIT 15NS 32SOJ |
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Negotiable |
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IS61(64)LF12832A |
Other |
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Negotiable |
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IS61(64)LF12836A |
Other |
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Negotiable |
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IS61(64)LF25618A |
Other |
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Negotiable |
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IS61(64)LPS12832A |
Other |
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Negotiable |
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IS61(64)LPS12836A |
Other |
Data Sheet |
Negotiable |
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IS61(64)LPS25618A |
Other |
Data Sheet |
Negotiable |
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