PSD854F290MI

PSD854F2-90MI, QFP64, memeory system, Waferscale, –0.6 to 14.0 V

Rated 5 Rating 5 | reviews | Write a review

Price:: US $10.32~33.46 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $10.32~33.46

PartNumber:: PSD854F290MI

Brand:: STMicroelectronics - ST | Pack: PLCC | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. hellen's store

(Hong Kong)

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2012-11-16

From Other Seller

Part Number:PSD854F290MI
US $10.32 - 33.46
EKZE250ELL152MK25S

US $0.10 - 1.00 / Piece
(0) Remove
ECA1HHG100

US $10.00 - 10.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The PSD854F290MI is a memory system for microcontrollers (MCUs). The PSD854F290MI brings In-System-Program- mability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. The PSD854F2-90MI combines many of the peripheral functions found in MCU based applications.

Parametrics

PSD854F290MI absolute maximum ratings: (1)TSTG, Storage Temperature: –65 to 125℃; (2)TLEAD, Lead Temperature during Soldering (20 seconds max.): 235℃; (3)VIO, Input and Output Voltage (Q = VOH or Hi-Z): –0.6 to 7.0 V; (4)VCC, Supply Voltage: –0.6 to 7.0 V; (5)VPP, Device Programmer Supply Voltage: –0.6 to 14.0 V; (6)VESD, Electrostatic Discharge Voltage (Human Body model): –2000 to 2000 V.

Features

PSD854F290MI features: (1)flash in-system programmable (ISP) peripheral for 8-bit MCUS; (2)dual bank flash memories: up to 2 mbit of primary flash memory (8 Uniform Sectors, 32K ×8); up to 256 Kbit secondary flash; (3)memory (4 Uniform Sectors); Concurrent operation: READ from one memory while erasing and writing the other; (4)up to 256 Kbit battery-backed SRAM; (5)27 reconfigurable I/O ports; (6)PLD with macrocells: Over 3000 Gates of PLD: CPLD and DPLD; CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs); DPLD - user defined internal chip select decoding; (7)27 individually configurable i/o port pins; (8)The can be used for the following functions: MCU I/Os; PLD I/Os; Latched MCU address output; Special function I/Os; 16 of the I/O ports may be configured as open-drain outputs.